Our veteran teams’ signal integrity experience with analog and high-speed digital designs is available as:

Signal Integrity Design and Analysis

• Architecture for clock and data distribution
• Crosstalk, coupling, and reflection control
• Timing analysis
• Skew and jitter reduction
• Suppression of simultaneous switching noise
• Mitigation of rise time degradation and inter-symbol interference effects
• VLSI package design or characterization
• Specification of design rules
• Simulation modeling

SPICE and IBIS model creation and validation

• Troubleshooting of existing SPICE and IBIS models
• Pre-layout and post-layout simulation
• Differential clock and data modeling
• 2-D field solver-RLCG matrix calculations

Transmission Line Analysis

• Selection of termination rules
• Controlled impedance calculation and impedance testing
• Skin effect, dielectric loss and dispersion control mitigation
• Long cable implementation
• EMI and EMC control