74ze Engineering's skills:

• Architecture development
• High-level modeling
• HDL coding (VHDL or Verilog)
• Design-for-Test
• Test-bench development
• Verification (strategy and implementation)
• FPGA prototyping
• Place and Route
• Floor-planning
• Test-Vector Generation
• PCB layout
• High-speed signal integrity analysis

Tools:

• Aldec Simulator:
  Active-HDL, CoVer, Riviera

• Cadence:
  NCVerilog, OrCad, SignalScan, Virtuoso Chip Assembly Router, LDV, DFII, PSpice, Allegro, SPECCTRAQuest

• MentorGraphics:
  Design Architect, Eldo, IC Station, HyperLynx

• Synopsys:
  Verilog-XL, VCS, VSS, DC Expert Plus, PrimeTime, TetraMax, TestGen, HSPICE

• Synplicity:
  Synplify (Pro), Amplify, Certify

• Altera:
  Max and Cyclone FPGAs

• Xilinx:
  Spartan and Virtex FPGAs, ChipScope

Languages:

Matlab, SPICE, C/C++, Pascal, Forth, Mathematica, Java
Verilog, VHDL, Vera, SpecMan, SystemC
Perl, Tcl/Tk, Ruby

Communication:

Complicated designs involving multiple teams require open and effective communication and intelligent risk management. Our project managers are senior engineers who are adept at maintaining project schedules and clear client communications.

Your technologies and trade secrets are kept in the strictest confidence. Always.